View THV3056_4721694.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

THV3056_rev.2.00_e 1/32 thine electronics, inc. copyright?2010 thine electronics, inc. description THV3056 is a 3ch buck/boost controller ic which enables to design simple & low cost multi-channel power supply system. ch-1(fixed boost), ch-2 a nd ch-3(fixed buck) are pwm controllers. as to ch-2, the output of 1.2v is available because the reference voltage of ch-2 is 0.85v. vgh and vgl are selectable positive/negative charge pumps and pfm controller. built-in high voltage ldo and vcom buffer amplifier facilitate to design various pow er supply systems for large scale tft panels. THV3056 achieves easy phase compensation even with a ceramic capacitor for the output. ss_1/2/3, ss_sw, dtc1/2/3, dtc_vgh/dtc_vgl and scp help to design user defined soft start time, dead time and timer latch delay time. two types of startup sequence are selectable by controlling sel1 pin. THV3056 is suitable for power supply system of tft lcd bias and system board with multi -channel power supply. 3ch buck/boost 2ch cp 1ch hvldo 1ch lvldo controller THV3056 qfn 64pin exposed pad (top view) 65gndexp nc v_out3 v_vgl out3 vcc inv_hldo out_vgl out_hldo xtest pgnd_cp pgnd3 out_vgh nc v_vgh vo_1in nc 52 59 49 50 51 58 57 56 54 55 60 53 63 62 61 64 32 20 27 17 18 19 26 25 24 22 23 28 21 31 30 29 ss_lldo bst2 vcfb v_lldo vcin out_lldo pgnd2 gndvc v_vc ll2 out_l2 vgl_uvp non_vgl inv_vgh out_h2 vcout tcon_xrst sgnd2 pg3 sgnd1 ss3 dtc2 vref ss2 dtc1 dtc_vgl dtc_vgh pg2 ss1 dtc3 pup_pg ss_sw 7 5 6 8 3 2 1 4 9 10 11 12 13 14 15 16 36 43 33 34 35 42 41 40 38 39 44 37 47 46 45 48 sel2 vo_1sw vreg5in vreg5 fb2 inv1 out1 inv3 scp fb1 rt syuvlo pgnd1 inv2 sel1 fb3 features ? qfn 64 pin package ? input voltage range : 4.2~ 15v ? push pull output for direct power mos driving ? ceramic capacitors are available for output ? complete pwm mode controller ? positive/negative charge pumps (selectable pfm mode) ? adjustable switching frequency up to 1mhz ? timer latch protection ? system uvlo function ? adjustable soft start time ? adjustable timer latch delay time ? adjustable dead time control ? thermal shutdown ? ch-1, boost converter ? ch-2, synchronous buck converter ? ch-3, boost/buck /inverting converter ? high voltage ldo ? ldo of 3.3v ? vcom buffer amplifier applications ? tft-lcd bias power supply pin assignment
THV3056_rev.2.00_e 2/32 thine electronics, inc. copyright?2010 thine electronics, inc. output channel description output channel description ch-1 pwm boost converter ch-2 pwm buck converter (nmos transistor drive for synchronous rec tifier / available for diode rectification) ch-3 pwm buck converter vgh positive charge pump selectable pfm mode hvldo high voltage ldo input voltage range : 6v to 17v vgl negative charge pump selectable pfm mode lvldo ldo of 3.3v input voltage range : 4.2 to 5.5v vo_1sw output for the external load switch. the load switch is soft-closed by sett ing capacitance conn ected to ss_sw pin. vcom buffer amplifier output voltage range : 1 to vo_1in-1v
THV3056_rev.2.00_e 3/32 thine electronics, inc. copyright?2010 thine electronics, inc. block diagram THV3056 tft multi channel controller inv3 ss2 scp out3 vcc vin sgnd1 dc det_1 osc fb2 inv2 out_h2 ss1 rt det_2 + - op + - comp vo2 vo3 vo3 + - comp osc out1 + - op + - comp vo1 fb1 inv1 vo1 ss3 dtc1 dtc3 vref vcc det_3 + - + - det_2 + - det_3 sysuvlo pg_2 pg_3 pg3 pg2 vo2 vref + - comp vo4 + - vref + - + - + - op vo1 + - v_lldo + - comp v_vc sgnd2 dtc2 vcout vo_1sw out_lldo out_vgh inv_vgh out_l2 ll2 bst2 out_vgl vreg5 pg_vgl + - vcfb non_vgl dtc_vgl + - pg_vgh + - pg_2 + - pg_ldo vref ovp ovp ovp ss_sw vreg5 vreg5 gndvc v_vgl + - op fb3 + - pg_3 vref v_vgh + - comp + - comp osc vref + - vo_1in out_hldo inv_hldo + - pg_hldo vref pup_pg vcin vreg5in xtest pgnd1 ss_lldo pgnd2 v_out3 pgnd3 vgl_uvp + - sel2 sel1 pg33 pg_vgh tcon_xrst 0.85v vref vref osc vref vref vref dtc_ vgh pgnd_cp sysuvlo cur_limit cur_limit vgh_ stop pup_pg p_good3 timer latch error detection p_good2 osc dtc_3 dtc_2 dtc_1 vref 0.01uf ss_3 2 ss_ ss_1 det_1 uvlo tsd 5vreg
THV3056_rev.2.00_e 4/32 thine electronics, inc. copyright?2010 thine electronics, inc. pin# symbol function description 10 12 14 fb1 fb2 fb3 ch-1,ch-2,ch-3 error amplifier output ch-1,2,3 error amplifier outputs for phase compensation by connecting resistors and capacitors be tween fb_1,2,3 and inv_1,2,3. 11 13 15 inv1 inv2 inv3 ch-1,ch-2,ch3 error ampli- fier inverting input ch-1,2,3 error amp inverting inputs . the voltage on inv1 and inv3 are 1.2v, and inv2 is 0.85v, in the normal operation. 18 19 20 ss1 ss2 ss3 ch-1,ch-2,ch-3 soft start soft start pin for ch-1/2/3. voltage at power-on is ground level. constant 1ma current source charges capacito rs connected to these pins. soft start time can be adjusted by extern al capacitors connected these pins. on/off control is available by c onnecting the external open drain ports or pg pins. 23 24 25 dtc1 dtc2 dtc3 ch-1,ch-2,ch-3 dead time control to limit the maximum duty cycle on ch-1,2,3. see functional descript ion ?dtc? for detail. 17 ss_sw ch-1 soft start of external pmos switch ch-1 external pmos switch for soft start. voltage at power-on is ground level. constant 1ma current source charges the capacitor con- nected to this pin. soft start time of pmos transistor to vo_1sw can be adjusted by external capacitors conne cted this pin. on/off control is available by connecting the external open drain ports or pg pins. 46 inv_vgh vgh comparator invert- ing input vgh comparator inverting input. the voltage on this pin is 1.2v in the normal operation. 48 non_vgl vgl comparator non- inverting input vgl comparator non-inverting input. the voltage on this pin is 0v in the normal operation. 26 27 dtc_vgh dtc_vgl vgh (charge pump +)control vgl (charge pump -)control vgh, vhl charge pump control pins. when the input voltage is high level, these pins are on state. low level, off state. using as charge pump, please set the duty cycle of 50%. in pfm mode, these pin operate as dtc. see functional descript ion ?dtc? for detail. 22 vref reference voltage reference voltage of 1.2v. connect th is pin with an ex ternal capacitor of 0.01uf for stability. the maximum load current is 1ma. 4 sel1 startup sequence select two type of startup sequence are se lectable by connecting sel1 pin to gnd or vreg5 pin. see functional description ?startup sequence?. 5 sel2 charge pump uvp timer latch on/off control charge pump uvp timer latch on/off control is available by sel2 pin. see functional descript ion ?scp? for detail. 41 v_vc voltage supply for vcom output voltage supply for vcom output. 47 vgl_uvp uvp voltage of vgl set pin uvp voltage can be set optionally by connecting an external resistor to this pin. without external resistor, uvp voltage is set at 50% of the ref- erence voltage. pin description
THV3056_rev.2.00_e 5/32 thine electronics, inc. copyright?2010 thine electronics, inc. pin# symbol function description 62 v_out3 output power supply for out3 output power supply for out3. 64 xtest test mode select connect to vcc in normal operation. 16 rt timing resistor for oscilla- tor resistor connection pin to set oscillation frequency. see functional descri ption ?oscillation ci rcuit? for detail. 21 29 sgnd1 sgnd2 signal gnd gnd for control circuit. 45 vcin vcom buffer amplifier non-inverting input vcom buffer amplifie r non-inverting input. 43 gndvc power gnd for vcom buffer amplifier power gnd for vcom buffer amplifier. 44 vcfb vcom buffer amplifier inverting input vcom buffer amplifie r inverting input. 42 vcout vcom buffer amplifier output vcom buffer amplifier output. connecting external bipolar transistor , it can accept high output current. 9scp timer latch short circuit protection setting the delay time of scp timer latch circuit. the delay time means the period from detection of abnorma l operations, to shut down of ic. see functional descrip tion ?short circuit protection? for detail. 31 28 pg2 pg3 power good output open drain output. connect an a pproximately 100k ohm pull-up resis- tor. during soft start, when the volta ge of ss pin rise up to the predeter- mined voltage(ch-2/1v, ch-3/1.35v), pg pin output goes high level. when soft start has finished normally, the output is fixed to high level. do not connect the pull-up resist or to higher voltage than vreg5. 32 pup_pg power good resistor connection pin connecting pg pins with external control pins and also shorting vcc pin and vreg5 pin, the resistor conne cted to pg pin should be pulled up to pup_pg pin. 2 40 54 59 pgnd1 pgnd2 pgnd_cp pgnd3 power gnd gnd for power circuit. 56 out_vgl vgl (charge pump -)output vgl drive output for negative voltage charge pump. v_vgl is used as input power supply. in pfm mode, th is pin can be used as pmos gate drive.
THV3056_rev.2.00_e 6/32 thine electronics, inc. copyright?2010 thine electronics, inc. pin# symbol function description 37 out_h2 ch-2 high side drive output ch-2 high side nmos transistor drive for synchronous rectifier. 36 bst2 ch-2 high side capacitor connection pin ch-2 power supply for high side drive output. 53 out_vgh vgh (charge pump +)output vgh drive output for positive voltage charge pump. v_vgh is used as power supply. in pfm mode, this pin can be used as nmos gate drive. 57 v_vgl vgl output voltage supply vgl output voltage supply. 58 v_vgh vgh output voltage supply vgh output voltage supply. 49 inv_hldo hvldo amplifier invert- ing input hvldo inverting input. the voltage on this pin is 1.2v in the nor- mal operation. 50 out_hldo hvldo output hvldo output. connect to an external capacitor(typ:2.2uf). 51 vo_1in hvldo voltage supply hvldo voltage supply. 34 ss_lldo lvldo soft start soft start pin for lvldo. 33 out_lldo lvldo output lvldo output. connect to an external capacitor(typ:10uf). 35 v_lldo lvldo voltage supply lvldo voltage supply. 3 vo_1sw ch-1 control output for switch ch-1 gate control output for the exte rnal switch. the voltage is in pro- portion to the voltage on ss_sw pin. 1 out1 ch-1 output ch-1 drive output for the external fet of boost. 0~5v 6 vreg5in voltage supply for control connect to vreg5 pin. 7 vreg5 5v regulator output power supply for low voltage output. connect this pin with an ex ternal capacitor (typ:4.7uf). 8 sysuvlo system uvlo input sysuvlo pin shuts down the ic, when the power supply voltage is lower than the predetermined voltage . vin voltage divided by resistance is applied. the mini mum operation voltage ca n be set optionally by changing the resistance value. if not in use, connect this pin to vref or vreg5 pin. 63 vcc power supply for control power supply for control. 39 out_l2 ch-2 low side driver out- put ch-2 low side nmos transistor drive for synchronous rectifier. available even without low side nmos transistor. but in this case, set the load current of ch-2 at more than 10ma. 38 ll2 ch-2 inductor node con- nection pin ch-2 inductor node connection pin. 61 out3 ch-3 output ch-3 drive output for an external fet of buck(push-pull). 0 v_out3 52 55 60 nc nc no connection. leave open. 65 gndexp back side gndexp should be soldered to gnd to improve the thermal character- istics.
THV3056_rev.2.00_e 7/32 thine electronics, inc. copyright?2010 thine electronics, inc. absolute maximum ratings parameter symbol rating unit input power supply voltage vcc 18 v inv1/2/3, inv_vgh/inv_ vgl, fb1/2/3, non_vgl, dtc1/2/3, dtc_vgh/dtc_vg l, ss1/2/3, ss_sw, pg2/3, sysuvlo, scp, sel1/2, vreg5in, vgl_uvp vl_in1 6.5 v bst2-ll2, out_h2-ll2 vl_in2 6.5 v xtest vh_in1 18 v vcin, vcfb vh_in2 20 v out1, vref, rt, out_l2, vreg5, pup_pg, tcon_xrst vl_out 6.5 v vcout, out_hldo, out_vgl, out_vgh, vo_1sw vh_out1 20 v ll2, out3 vh_out2 18 v v_vgl, v_vgh, v_out3, v_vc vh_cc 20 v bst2, out_h2 vh_out3 24 v output current out1, out_l2, out_h2, out3, out_vgh, out_vgl iomax 1 a output current out_hldo iomax2 80 ma power dissipation pd 4125 (ta<25 c) mw junction temperature tj 150 c operating temperature ta -40 c +85 c storage temperature tstg -55 c +150 c lead temperature for soldering tlead 255 / +5 / -0 / 10sec c power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 -40 -20 0 20 40 60 80 100 120 140 160 ambient temperature ta() allowable power dissipatio n pd(mw)
THV3056_rev.2.00_e 8/32 thine electronics, inc. copyright?2010 thine electronics, inc. recommended operating condition parameter min typ max unit vcc voltage(input power supply voltage) 4.2 15 v vreg5,vreg5in voltage 4.2 5.5 v ll2, v_out3 voltage 4.2 17 v v_vgh, v_vgl voltage 4.2 17 v vo_1in, v_vc voltage 5.5 17 v v_lldo 4.2 5.5 v bst2, out_h2 voltage -0.1 20 v out3 voltage -0.1 17 v vo1_sw, vcfb, vcout, vcin, out_hldo, out_vgh, out_vgl -0.1 17 v out1, sysuvlo, inv1/2/3, inv_vgh, i nv_hldo, dtc1/2/3, dtc_vgh, dtc_vgl, pg2,3 out_l2, vreg5, pup_ pg, vgl_uvp, sel1,2 voltage -0.1 5.5 v fb1/2/3, ss1/2/3, ss_ll do, vref, rt voltage -0.1 3 v out_lldo, tcon_xrst voltage 3.3 v external capacitance for vref pin 0.01 uf external capacitance for vreg5 pin 2.2 4.7 uf external capacitance for out_hldo pin 1 2.2 uf out_hldo output current 10 ma external capacitance for out_lldo pin 10 uf out_lldo output current 300 ma oscillation frequency 200 1000 khz x_test voltage vcc v
THV3056_rev.2.00_e 9/32 thine electronics, inc. copyright?2010 thine electronics, inc. parameters symbol condition min typ max unit reference voltage block reference voltage vref cvref = 0.01uf 1.188 1.2 1.212 v reference voltage(ch-2) vref(ch2) vref x 0.85/1.2 0.841 0.85 0.859 % temperature coefficient vref(tc) iref = -100ua, ta = -40 ~ 85 c 0.5 % line regulation vref(line) iref = -100ua, vcc = 4.2 ~ 15v 2 5 mv load regulation vref(load) iref = -100ua ~ -1ma 25mv oscillator circuit block oscillation frequency fosc rt = 47k 460 500 540 khz temperature coefficient fosc(tc) ta = -40 ~ +85 c 5 % dtc circuit block maximum duty cycle (ch-1,3) dmax (ch-1,3) 89 % maximum duty cycle(ch-2) dmax(ch-2) 85 % maximum duty cycle (vgh) dmax (vgh) 93 % maximum duty cycle (vgl) dmax (vgl) 87 % error amplifier block offset voltage vio1,vio3 based on vref pin voltage -10 10 mv vio2 buffer connection based on the value : vref x 0.85/1.2 open loop gain vav 70 db unity gain bandwidth bw 1.5 mhz output sink current isnk vfb = 1.0v 40 100 ua output source current isrc vfb = 1.0v 1 3 ma ss offset voltage vsso 0.2 v charge pump block threshold voltage (vgh) vthc(vgh) 1.2 v threshold voltage (vgl) vthc(vgl) 0 v offset voltage(vgh/vgl) vioc (vgh/vgl) -20 20 mv electrical characteristics (at vcc = 12v, rt= 47kohm, ta = 25c , unless otherwise noted )
THV3056_rev.2.00_e 10/32 thine electronics, inc. copyright?2010 thine electronics, inc. parameters symbol condition min typ max unit high voltage ldo block offset voltage vhvldo(off) ildo = -1ma -20 20 mv load regulation vhvldo(load) vo_1in = 16v, out_hldo = 15v ildo = -0.1m ~ -2ma 15 40 mv high side output voltage range vhldo(hrange) ildo = -10ma vo_1in -0.5 vo_1in -0.2 v low side output voltage range vh ldo(lrange) ildo = -10ma 5.5 v dropout voltage vdrop(hldo) ildo = -10ma,vo_1in = 16v, inv_hldo = 0v 0.18 0.35 v low voltage ldo block output voltage vout(lldo) iout_lldo = 200ma 3.2 3.3 3.4 v load regulation vlldo(load) 1ma < iout_lldo < 300ma 33 mv line regulatio n vlldo(line) 4.2v < v_lldo < 5.5v iout_lldo = 200ma 10 mv dropout voltage vdrop(lldo) v_lldopin iout_lldo = 200ma, vout = 3.2v 3.3 v v com buffer amplifier block offset voltage vvcom(off) vo_1in = 15v, vcin = 5v -10 10 mv load regulation vvcom(load) io = 0 ~ 5ma -50 50 mv line regulation v vcom(line) vo_1in = 6v ~ 17v 2 10 mv input common mode voltage range vvcom(range) r l = 10k 1 vo_1in -2 v output source maximum load current ivcomh(max) 30 70 ma output sink maximum load current ivcoml(max) 30 70 ma input bias current iib(vcom) 0.5 2.5 ua 5v regulator block output voltage vreg5(range) io = -1ma 5.0 v load regulation vreg5(load) io = -0.1ma ~ -5ma 100 mv line regulation vreg5( line) io = -1ma, vcc = 5.5v ~ 15v 20 mv soft start block ss1,2,3 charge current iss vss = 0.5v 0.6 1.0 1.4 ua ss_sw charge current isssw vss_sw = 0.5v 1 ua ss_lldo charge current i sslldo vss_lldo = 0.5v 1 ua
THV3056_rev.2.00_e 11/32 thine electronics, inc. copyright?2010 thine electronics, inc. parameters symbol condition min typ max unit switch control block output voltage for load switch vo( vo_1in) vss_sw = 1.2v, v_vgl = 18v 15 v output resistance for vo_1sw ro(vo_1sw) io = 1ma, ss_sw = 2.5v 1.2 k power good block output resistance ropg pg = low io = 1ma 0.9 1.6 k pup_pg output resistance rpup_pg io = -1ma 0.4 k ss2 threshold voltage vpgss2 1 v ss3 threshold voltage vpgss3 1.35 v inv_vgh, inv_hldo threshold voltage vpg_vgh,hldo 1.02 v non_vgl threshold voltage vpg_vgl 0.18 v out_lldo threshold voltage vpg_lldo out_lldo pin 2.64 v vgl_uvp block vgl_uvp threshold voltage vuvp_vgl 0.6 v vgl_uvp pin input resistance ri(vgl_uvp) 500 k output block out1 h level output resistance roh(ch-1) ioh = -50ma 17 out1 l level output resist ance rol(ch-1) iol = 50ma 11 out_h2 h level output resistance roh(ch-2h) ioh = -50ma 17 out_h2 l level output resistance rol(ch-2h) iol = 50ma 13 out_l2 h level output resist ance roh(ch-2l) ioh = -50ma 17 out_l2 l level output resist ance rol(ch-2l) iol = 50ma 6 out3 h level output resistance roh(ch-3) ioh = -50ma 13 out3 l level output resist ance rol(ch-3) iol = 50ma 7 out_vgh h level output resistance roh(vgh) v_vgh = 15v, ioh = -50ma 10 out_vgh l level output resistance rol(vgh) v_vgh = 15v, iol = 50ma 9 out_vgl h level output resistance roh(vgl) v_vgl = 15v, ioh = -50ma 26 out_vgl l level output resistance rol(vgl) v_vgl = 15v, iol = 50ma 16 tcon_xrst h level output resistance roh(xrst) out_lldo = 3.3v, iol = -50ma 14 tcon_xrst l level output resistance rol(xrst) out_lldo = 3.3v, iol = 50ma 24
THV3056_rev.2.00_e 12/32 thine electronics, inc. copyright?2010 thine electronics, inc. parameters symbol condition min typ max unit over voltage protection block threshold voltage (ch-1, ch-3) vovp (ch-1,ch-3) inv1/inv3 pin 1.5 v threshold voltage (ch-2) vovp(ch-2) inv2 pin 1.063 v uvlo block on threshold voltage(vcc) vuvlo v cc pin(h>l), ivreg5 = -1ma 2.54 v hysteresis voltage(vcc) vuvlo( hys) vcc pin, ivreg5 = -1ma 200 mv on threshold voltage (vreg5in) vuvlo vreg5in pin (h>l) 2.55 v hysteresis voltage (vreg5in) vuvlo_vreg5 (hys) vreg5in pin 239 mv system uvlo block on threshold voltage vsysuvlo s ysuvlo pin(h>l) 0.97 1.00 1.03 v hysteresis voltage vsysuvlo(hys) sysuvlo pin 0.13 0.22 0.31 v timer latch block threshold voltag e vlat scp pin 1.15 1.20 1.25 v charge current (uvp) iscp(uvp) vscp = 0.1v 0.6 1.0 1.4 ua charge current (ovp) iscp(ovp) vscp = 0.1v 3.0 5.0 7.0 ua scp reset voltage vscp(rst) vcc pin 1.6 v control block sel1/sel2 h level threshold voltage vsel1(h) vsel2(h) vreg5in - 0.5v vreg5in v sel1/sel2 l level threshold voltage vsel1(l) vsel2(l) 00.5v overall average current consumption icc(op) output swing on (vcc) 4.5 9.0 ma icc output swing off, ss_1/2/3 = 0v, dtc_1/2/3,dtc_vgh, dtc_vgl = 0v (vcc) 3.5 7.0 ma
THV3056_rev.2.00_e 13/32 thine electronics, inc. copyright?2010 thine electronics, inc. system uvlo system uvlo stops ic operation when the input voltage decreases less than the user defined voltage. uvlo(undervoltage lockout) prevents the device from the malfunction under the lower vcc voltage at which ic can not operate normally. however in the actual system board, it is often required not to operate dc/dc controller ic under the voltage which is defined by the individual system, even if the voltage is enough high for normal operation of the ic. utilizing system uvlo function, it is able to control the ic operation only with two external resistors. the below figure 1 shows the example set at more than 4.0v(vin), and figure 2 shows the operation example of system uvlo. after input power supply voltage(vin) rises up to the releas e voltage of uvlo(4.27v in th is example), the soft start operation starts and the voltage on ss pin rises gradually. wh en the voltage reaches to 1.2v , soft start operation is fin- ished and the output voltage reaches to the user defined voltage. when input power supply voltage(vin) drops to the system uvlo detection voltage (under 3.5v in this example), sys- tem uvlo stops all switching operations instantly and the vol tage on ss pin will be pulled down to gnd level. as switch- ing operation stops, the output voltage decreases. the shut off mode by the detection of system uvlo will be released, when vin exceeds the system uvlo release voltage. (see figure 2) generally input power supply voltage(vin) decreases when the output short circuit or over load.are detected. the decrease of input power supply voltage resets the scp. please pay attention of setting the system uvlo voltage and the scp timer latch delay time. note1) please set the system uvlo voltage and scp delay time in order that the shut off by scp works earlier than system uvlo operation. otherwise, the foll owing operation will be repeated: output short-circuit power-supply voltage d ecrease (uvlo operation) shut off by system uvlo short-circuit current decrease power-supply voltage rise (uvlo release) out put short circuit remaining power-supply voltage decrease shut off by system uvlo if system uvlo is not required, co nnect sysuvlo pin with vref or vreg5 pin. in that case, only inte rnal uvlo circui t will operates. vcc vin sysuvlo r1 r2 82k 33k functional description release voltage of system uvlo detection voltage of system uvlo 1.22 r1 r2 + r2 ------------------ - ? 1.0 r1 r2 + r2 ------------------ - ? figure 1. system uvlo setting example
THV3056_rev.2.00_e 14/32 thine electronics, inc. copyright?2010 thine electronics, inc. figure 2. system uvlo operation example uvlo if system uvlo is not in use, the internal uvlo circuit will operates. the detection voltage is set at 2.54v, and the release voltage is set at 2.74v. note 2) when not in use, connect sysuvlo pin to vref pin or vreg5 pin. ss vin vo switching 1.20v operating stop operating stop 2 2 1 r r r ? 1.22 (v) 1.0 (v) 2 2 1 r r r ? 4.27v 3.50v
THV3056_rev.2.00_e 15/32 thine electronics, inc. copyright?2010 thine electronics, inc. soft start THV3056 has soft start circuit to prevent high inrush curr ent of the dc/dc converter du ring start up. ss pins are internally connected to 1ua constant current source and nmos pull-down transistor. soft start time is set by the external capacitor connected between each ss pins and gnd. pull-down transistor is in the on state and the voltage on ss pins are set at gnd level, until system uvlo or uvlo is released. on/off control on each channels are available by connecting ss pins to the exte rnal open-drain driver. (see figure 3) error amplifier has three inputs of pmos transistor, one in verting and the others non-inverting. one of non-inverting inputs is connected to ss pin and the other is connected to in ternal reference voltage. the reference voltage is 1.2v for ch- 1 and ch-3, 0.85v for ch-2. th e voltage on ss pin gradually rises up from gnd level and then exceeds the reference volt- age. the lower voltage one is active between two non-inverting inputs using pmos transistors. thus the input from ss pin is active if the voltage is under 1.2v for ch-1 and ch-3, 0.85v for ch-2. also the input from internal reference voltage is active if the voltage on ss pin exceeds 1. 2v for ch-1 and ch -3, 0.85 for ch-2. during soft start operation, ss pin is act ive and the dc/dc converter operates at the voltage on ss pin as the reference voltage. the gradual voltage increase on ss pin is equivalent to the gradual increase on the reference voltage and output voltage. soft start operation is comple ted when the voltage on ss pin reaches to the internal reference voltage. soft start time, tss, is calculated as following : when , for ch-1 and ch-3/ for ch-2. different from dtc type, this type of soft start provides a natural rising-up waveform without overshooting. soft start time is defined only by the external capacitor and output voltage rises up in proportion to the gradual voltage rising up on ss pin. also the sequence settin g is easy because it doesn?t depend on the load current fluctuation at the power on, and that facilitate the setting of sequences. please note that the po wer on during output short circuit causes instant maximum duty operation, because the control circuit recognize that the output voltage doesn ?t reach to the user defined set voltage. (see functional description ?dtc? for detail) pg pg pins are open-drain outputs of nmos pull-down transist or. when the power supply is turned on, nmos transistor is on and the voltage on pg pin is gnd level. when the voltage on ss2 pin reaches to approx imately 1v for ch-2, ss3 pin reaches 1.35v for ch-3, nmos transistor is turned off. when pg pins are connected to external control pins, resistor con- nection pins must be set accord ing to the power supply voltage. table 1 pg resistor connection connecting pg pins to vcc through approximately 100kohm pull-up resistor, the output voltage on pg pins rises up to high level when output voltage reaches more than 90% of user defined voltage. th ose output signals can be utilized for other external circuits, but do not connect to the pull-up resistor to the higher voltage than vreg5. power supply voltage resistor connection pin under 5.5v pup_pg higher than 5.5v vreg5 tss 1,3 P 6 10 1 2 . 1 ? ? = 1.2 6 10 css (sec) tss2 P 6 10 1 85 . 0 ? ? = 0.85 6 10 css (sec) css P 0.01uf tss P 12ms tss P 8.5ms
THV3056_rev.2.00_e 16/32 thine electronics, inc. copyright?2010 thine electronics, inc. figure 3. block diagram for sequence using ss and pg 1.19v vref 1ua + - + fb_2 uvlo ss2 inv2 vref 1ua + - + fb_3 uvlo ss3 inv3 + - comp-2 pg2 + - comp-3 pg3 css2 css3 latch 1.0v
THV3056_rev.2.00_e 17/32 thine electronics, inc. copyright?2010 thine electronics, inc. low voltage ldo(of 3.3v output ) figure 4 shows the circuit diagram of low voltage ldo. applies the voltage of 5v to v_lldo pin and outputs 3.3v. when using the external 3.3v without ldo, short- circuit v_lldo pin and out_lldo pin and apply 3.3v. figure 4. low voltage ldo circuit tcon reset circuit tcon reset circuit generates a signal of high level, when the startup of out_lldo a nd vgh are completed normally. (see figure 5, figure 6.) figure 5. tcon reset circuit vref vgh_ok 80% out_lldo (output for 3.3v ldo) tcon_xrst vref12 v_lldo (5v input) out_lldo (output for 3.3v ldo) ss_lldo 1ua clam p circuit P 2.2v 1.2v
THV3056_rev.2.00_e 18/32 thine electronics, inc. copyright?2010 thine electronics, inc. setting - 1 vin=12v, using internal sw_reg of 3.3v. setting - 2 vin=125v, using 3.3v generated from ch-3. figure 6. startup sequence waveform startup sequence setting sel1 pin facilitate the startup sequence setting.(see table 2, figure 6.) ch2 lv-ldo ch1 vgl ch3 vgh vls(after sw) hv-ldo tcon reset signal ch2 ext 3.3v sw-reg ch1 vgl vls(after sw) hv-ldo ch3 vgh tcon reser signal ch2 3.3v ch3 ch1 vgl vgh tcon reset signal vls(after sw) hv-ldo
THV3056_rev.2.00_e 19/32 thine electronics, inc. copyright?2010 thine electronics, inc. table 2 sel1 pin setting sel1 connection startup sequence gnd setting - 1 vreg5 setting - 2 dtc(dead time control) dead time is set by applying voltage to dtc pins. it prevents the ic from getting into 100% on duty cycle and can set preferable maximum duty cycle for in dividual system requirement. about relationship between the dead time and the voltage on dtc pin, refer to typical characteristics described la ter. if not in use, connect dt c pin directly with vref pin or vreg5 pin. (see figure 7 (a)(b)) when ch-4,6 are used as charge pumps, set those outputs at 50% duty cycle (approximately 750mv). when used as pfm regulator, soft start can be set by connecting capacitors between dtc pins and gnd. (see figure 7(c)) the maximum duty cycle of ch-1,3 are internally set at 89%, ch-2 85%, vgh 93%, vgl 87%. figure 7. voltage apply example for dtc pin vgl-uvp circuit vgl-uvp circuit detects abnormal drops of output voltage cau sed by short circuits or over load. the internal vgl-uvp comparator monitors the output voltage of non_vgl and comp are with the value of vref which is divided in half by resistor. the division value of vref can be set even by the external resist or.(see figure 8.) connect a capacitor of 0.01uf to vgl_uvp pin without using external resistor. if th e output voltage drops below the user defined voltage, the system goes into max duty cycle and uvp comparator stop s vgh and reports the abnormal output of charge pump to scp circuit. figure 8. vgl_uvp circuit atypical vref dtc pin vref or vreg5 dtc pin bmaxdutyinternally set r1 r2 33k 56k dtc pin cpfm regulatorvgh/vgl vref delay stop signal for vgh 1m 1m vgl vref(1.2v) vref12 vgl_uvp non_vgl uvp comparator vref(1.2v) r1 r2
THV3056_rev.2.00_e 20/32 thine electronics, inc. copyright?2010 thine electronics, inc. table 3 sel2 pin setting sel2 connection startup sequence gnd c.p timer latch/active vreg5 c.p timer latch/inactive short circuit protection scp timer circuit scp shut down the ic operation when the max duty operation/ovp operation /abnormal temperature continue for a longer time than the user defined time. scp timer circuit has th e internal constant source curr ent circuit, a pull-down tran- sistor and an external capacitor connected between scp pin and gnd. in the normal operation the internal pull-down tran- sistor is in on state, and scp pin is held gnd level. (see figure 9.) when uvp comparator detects the output voltage drop, the pull- down transistor connected with scp pin is turned to off and the external capacitor is charged with 1ua constant current. wh ile ovp comparator detects the output voltage rise or the abnormal temperature is detected continuously, the voltage on scp pin keep on rising in proportion to the time con- stant defined by 5ua cons tant current and the external cap acitor. when the voltage on scp pin reaches to 1.2v, the latch operates and then all channels stops and goes into shut dow n mode. (see figure 10.) the latch state will not be released until power supply is restarted. the delay time to the latch state can be set by the external capacitance. also, users can select scp timer mode(on/ off) of charge pump by sel2 pin.(see table 3.) the delay time tscp is given by following : when cscp=0.01uf and uvp is activated, the scp delay time (tscp) is around 12msec. also, when ovp or tsd is acti- vated, tovp is around 2.4msec. in the case of uvp, in the case of ovp or tsd, note 1) when output short circuit or ov er load occur, the input power supply voltage (vin) ma y decrease according to the circumstances. uvlo resets scp timer latc h state, so please set the delay time in order that timer latch works earlier than uvlo operation. otherwise, the follo wing operation will be repeated: output short-circuit power-supply voltage d ecrease (uvlo operation) short-circuit cu rrent decrease power-sup- ply voltage rise (uvlo release) power-supply voltage decrease note 2) when uvp timer latch function of charge pump is set to be enable, please be careful to determine the delay time considering the startup time of charge pumps. (see figure 11.) tscp 1.2 1 6 ? ? 10 ---------------- - cscp 1.2 6 ? 10 cscp sec ?? ? = ? = tovp 1.2 5 6 ? ? 10 ---------------- - cscp 2.4 5 ? 10 cscp sec ?? ? = ? = uvp(under volt age protection) uvp circuit detects abnormal drops of output voltage caused by short circuits or over load. the internal uvp comparator monitors the output voltage of error amplifiers(fb1,2,3). in the normal operation the inverting input voltage is approximately 1.2v, same as the non-inverting input connected internally to vref. the invert- ing input voltage decreases in proportion to the output volta ge drop. if the output voltage drops below the user defined voltage, the system goes into max duty cycle and uvp comparator reports the abnormal oper ation of dc/dc converter to scp circuit. (see figure 9)
THV3056_rev.2.00_e 21/32 thine electronics, inc. copyright?2010 thine electronics, inc. figure 10. scp operation waveform + - error amp latch vref ss + - 1.58v scp reset + - 1.2v 1a scp maxduty-detector vout cscp ss vo switching scp 1.2v 1.2v operating stop timer latch operation
THV3056_rev.2.00_e 22/32 thine electronics, inc. copyright?2010 thine electronics, inc. figure 11. charge pump scp operation waveform over voltage protection(ovp) ovp circuit stops the output, if the output voltage on ch-1/2/3 exceed the pr edetermined voltage. the internal ovp comparator (with reference voltage of 1.5v for ch-1 and ch-3, 1.06v for ch-3) monitors the voltage on inv pins. the output of ovp comparator is connected to out pin. when the voltage on inv pin exceeds 1.5v for ch-1 and ch-3, 1.06v for ch-2, out pin turns external mos transistor off and stops switching operation to prevent the output voltage excessing the predetermined voltage.(s ee figure 12.) also, ovp comparator of ch-2 and ch-3 report the abnormal operation to scp circuit. figure 12. ovp circuit note) operation at fb - inv short circuit when fb pin and inv pin are short circuited, the internal constant current circuit (100ua) affects the output voltage. an approximate output voltage is given by the following formula. the output voltage at fb-inv short circuited(vout) = the normal output voltage x 1.25 + rh x 100ua also, ovp comparator has delay circuit of 0.5us to prevent th e malfunction, so the actual output voltage will be higher than the result of calculation. scp vgh/vgl 85% 85% latch voltage=1.2v scp latch time >> vgh/vgl startup time + - error amp vref + - ovp comp vout pwm comp out fb inv rh 100ua ch1, ch-3=1.5v ch-2=1.06v
THV3056_rev.2.00_e 23/32 thine electronics, inc. copyright?2010 thine electronics, inc. figure 13. output voltage setting output voltage setting figure 13 shows ch-1 output voltage setting model. the voltage on inv1 pin is equal to the voltage on vref pin due to the effect of feed-back. the voltage on inv_1 pin is the divided voltage of vout by r1 and r2. so, therefore, since vref =1.2v, then similarly the output voltage of ch-2 and ch-3 is described as follows. vout1 r2 r1 r2 + ------------------ - ? vref = vout1 vref 1 r1 r2 ----- - + ?? ?? ? = vout1 1.2 1 r1 r2 ----- - + ?? ?? ? = vout2 0.85 1 r4 r5 ----- - + ?? ?? ? = vout3 1.2 1 r7 r8 ----- - + ?? ?? ? = c1 fb1 inv1 vout1 r2 r3 r1 + - error amp1 vref =1.2v pwm comparator fb2 inv2 vout2 r5 r6 r4 + - error amp2 c3 c2 c4 fb3 inv3 vout3 r8 r9 r7 + - c6 c5 erroramp3 vref =1.2v vref =0.85v pwm comparator pwm comparator
THV3056_rev.2.00_e 24/32 thine electronics, inc. copyright?2010 thine electronics, inc. description of charge pumps. as to vgh, the voltage on inv_vgh pin is controlled to be equal to the voltage of vref. (see figure 14.) the voltage on inv_vgh pin is the divided voltage of vgh by r9 and r10. so vgh vref 1 r9 r10 -------- - + ?? ?? ? 1.2 1 r9 r10 -------- - + ?? ?? ? == figure 14. output setting for vgh figure 16. output setting for inverting mode figure 15. output setting for vgl as to vgl, the voltage on non_vgl pin is controlled to be zero. (see figure 15, figure 16.) the current through non_vgl is negligible. therefore vgl vref ?? ? r11 r12 -------- - ? 1.2 ? r11 r12 -------- - ? == inv_vgh vgh r10 r9 + - comp1 vref =1.2v output circuit non_vgl vgl r12 r11 + - comp1 output circuit vref =1.2v r11 vref1.2v r12 vgl 0v
THV3056_rev.2.00_e 25/32 thine electronics, inc. copyright?2010 thine electronics, inc. voltage reference circuit voltage reference circuit generates temp erature-compensated voltag e(=1.2v) for the use as the internal reference voltage. also, an external load curren t can be obtained from the power supply at vref pin, up to 1ma maximum. please connect a capacitor of 0.01uf betw een vref pin and sgnd for stability. error amplifier error amplifier detects the output voltage of switching regulator and outputs the pwm control signal. programmable by connecting feedback resistor and capacitor between the output of error amp(fb_1/2/3) and inverting input(inv_1,2), it can provide stable phase compensation. oscillation circuit the oscillation frequency can be defined by the external resistor connected between rt pin and gnd. (see typical characteristics ?the graph of oscill ation frequency vs rt resistance?.) the relation between the oscillation frequency and th e resistance of rt is approximately as follows. oscillation frequency khz P vreg5, vreg5in built-in 5v local regulator for power supply of ch-1 and ch-2 output and for internal power supply. if the input volt- age is lower than 5.5v, short-circuit the input voltage and vreg5 pin. if the input voltage is higher than 5.5v, leave the input voltage and vreg5 pin open. amplifier for vcom a buffer amplifier attained 4v/us slew rate. if output current is required, use the external bipolar transistor. thermal shut down(tsd) tsd detects abnormal heat and reports it to scp circuit. the detecting temperature is 175 c , release temperature is 160 c. current limit circuit(ldo) high voltage ldo and low voltage ldo( of 3.3v output) have built-in auto-recovery current limit function. the thresh- old current is 250ma for high voltage ldo, 700ma for low voltage ldo. rt(k ) 2.35 x 10 4
THV3056_rev.2.00_e 26/32 thine electronics, inc. copyright?2010 thine electronics, inc. 460 480 500 520 540 -50 0 50 100 150 ambient temperature[] oscillation freq uency[khz] 1.190 1.195 1.200 1.205 1.210 -50 0 50 100 150 ambient temperature[] vref[v] 0 200 400 600 800 1000 1200 0 50 100 150 rt[kw] oscillation frequency[khz] 460 480 500 520 540 0 5 10 15 20 vcc[v] oscillation freq uency[khz] 1.190 1.195 1.200 1.205 1.210 0 5 10 15 20 vcc[v] vref[v] 1.190 1.195 1.200 1.205 1.210 00.51 iref[ma] vref[v] typical c haracteristic s oscillation frequency vs rt resistance oscillation frequenc y vs vcc voltage oscillation frequency vs ambient temperature vref vs vcc voltage(line regulation) vref vs iref (load regulation) vref vs ambient temperature
THV3056_rev.2.00_e 27/32 thine electronics, inc. copyright?2010 thine electronics, inc. 0 1 2 3 4 5 -50 0 50 100 150 ambient temperature[] icc[ma] 0.0 0.5 1.0 1.5 -50 0 50 100 150 ambient temperature[] scp charge current[ua] 0.0 0.5 1.0 1.5 -50 0 50 100 150 ambient temperature[] soft start charge current[ua] 0 1 2 3 4 5 0 5 10 15 20 vcc[v] icc[ma] 0 2 4 6 -50 0 50 100 150 ambient temperature[] ovp charge current[ua] 0 20 40 60 80 100 0.40.50.60.70.80.9 1 vdtc(v) duty(%)
THV3056_rev.2.00_e 28/32 thine electronics, inc. copyright?2010 thine electronics, inc. 0 10 20 30 40 -50 0 50 100 ambient temperature[] roh[] 0 10 20 30 40 -50 0 50 100 ambient temperature[] roh[] 0 5 10 15 20 -50 0 50 100 150 ambient temperature[] roh[] 0 5 10 15 20 -50 0 50 100 150 ambient temperature[] rol[] 14.5 15.0 15.5 16.0 0 10203040 output current[ma] out_hldo [v] 3.0 3.1 3.2 3.3 3.4 0 100 200 300 output current[ma] out_lldo [v]
THV3056_rev.2.00_e 29/32 thine electronics, inc. copyright?2010 thine electronics, inc. -400 -200 0 200 400 600 800 time[us] io[ma] v_hvldo[mv] 10a/di v 10v/di v time[us] vo5[v] vo_1in[mv] 10v /di v 15.6v 15.2v 0510 0.0 0.5 1.0 1.5 2.0 -50 0 50 100 150 ambient temperature[] vcomamp input bias current[ua] -100 0 100 200 300 time[us] io[ma] v_lvldo[mv] 100ma/div 20mv/div
THV3056_rev.2.00_e 30/32 thine electronics, inc. copyright?2010 thine electronics, inc. package outline side view bottom view 6.800.10 0.50 bsc. 0.230.05 0. 500.05 0.60 9.00 bsc. 9. 00 bsc. 1 pin index 0.45 pin1 id r 0.20 seating plane 0.20 ref. 0.90 max 0.650.70 0.05 max detail 0.05 0.500.05 unit : mm 0.61 r 0.09 min. 6.800.10 s s 64 top view 64
THV3056_rev.2.00_e 31/32 thine electronics, inc. copyright?2010 thine electronics, inc. recommended land pattern design following shows the recommended land pattern design for qfn64pkg. *this land pattern is for refere nce purpose only. please examine ca refully at deigning the board. unit : mm c 0.3 7.1 7.1 9.6 0.95 0.23 0.5 9.6 0.72 0.95 0.95
THV3056_rev.2.00_e 32/32 thine electronics, inc. copyright?2010 thine electronics, inc. notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be fo und in this mate rial, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other propr ietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership should occur by using this product, we will be exempted from the responsib ility unless it directly re lates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (including medical equi pment directly concerning people's life, aerospace equipment, or nuc lear control equipment). also, wh en using this product for the equipment concerned with the control and safety of the transportation m eans, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriate measures to the product. 6. despite our utmost efforts to imp rove the quality and reliability of the product, fa ults will occur with a certain small probability , which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficient ly redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by them selves if this product falls under the category of strategic goods under the foreign exch ange and foreign trade control law. 9. the product or peripheral parts may be damaged by a surge in vol tage over the absolute maxi- mum ratings or malfunction, if pins of the product are s horted by such as foreign substance. the damages may cause a sm oking and ignition. therefore, you are encouraged to implement safety measures by adding protecti on devices, such as fuses. thine electronics, inc. e-mail : sales@thine.co.jp

▲Up To Search▲

Price & Availability of THV3056

	To Download THV3056 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .